Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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12/11/2001
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Application #:
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09747233
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Filing Dt:
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12/26/2000
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Inventor:
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Jeffrey S. Earl
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Title:
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Test mode for verification of on-chip generated row addresses
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| SCIENCE-BASED INDUSTRIAL PARK |
| 123, PARK AVE.-3RD |
| HSIN-CHI, TAIWAN R.O.C |
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| GEORGE O. SAILE |
| 20 MCINTOSH DRIVE |
| POUGHKEEPSIE, NY 12603 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| NO.8, LI-HSIN ROAD. 6, SCIENCE-BASED INDUSTRIAL PARK |
| HSIN-CHU, TAIWAN 300-77 |
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| THOMAS, KAYDEN, HORSTEMEYER & RISLEY, LL |
| 400 INTERSTATE NORTH PARKWAY SE |
| SUITE 1500 |
| ATLANTA, GA 30339 |
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