Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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01/15/2002
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Application #:
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09281232
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Filing Dt:
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03/30/1999
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Inventors:
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SHINKICHI GAMA, TAKESHI NAGASE, YOSHIKI OKUMURA, TOMOHIRO HAYASHI et al
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Title:
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Memory unit and buffer access control circuit for updating an address when consecutively accessing upper and lower buffers
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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NAKAHARA-KU, KAWASAKI-SHI |
1-1, KAMIKODANAKA 4-CHOME |
KANAGAWA 211-8588, JAPAN |
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STAAS & HALSEY |
H.J. HAAS |
700 ELEVENTH STREET, N.W., SUITE 500 |
WASHINGTON, D.C. 20001 |
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