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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
Issue Dt:
02/19/2002
Application #:
09597887
Filing Dt:
06/19/2000
Inventors:
Satish D. Athavale, Gary B. Bronner, Ramachandra Divakaruni, Ulrike Gruening et al
Title:
PROCESS FOR 4F2 STC CELL HAVING VERTICAL MOSFET AND BURIED-BITLINE CONDUCTOR STRUCTURE
Assignment: 1
Reel/Frame:
010926/0227Recorded: 06/19/2000Pages: 3
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
05/25/2000
Exec Dt:
05/25/2000
Exec Dt:
05/25/2000
Exec Dt:
05/30/2000
Exec Dt:
05/25/2000
Assignee:
NEW ORCHARD ROAD
ARMONK, NEW YORK 10504
Correspondent:
POLLOCK, VANDE SANDE & AMERNICK
ERIC J. FRANKLIN
1990 M STREET, N.W., SUITE 800
WASHINGTON, D.C. 20036-3425
Assignment: 2
Reel/Frame:
010926/0239Recorded: 06/19/2000Pages: 3
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
06/13/2000
Assignee:
1730 NORTH FIRST STREET
SAN JOSE, CALIFORNIA 95112
Correspondent:
POLLOCK, VANDE SANDE & AMERNICK
ERIC J. FRANKLIN
SUITE 800
1990 M STREET, N.W.
WASHINGTON, D.C. 20036-3425

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