Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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05/21/2002
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Application #:
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09474872
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Filing Dt:
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12/29/1999
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Inventor:
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JONG-HEE HAN
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Title:
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REDUCED POWER BIT LINE SELECTION IN MEMORY CIRCUITS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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BUBAL-EUB, ICHON-SHI |
SAN 136-1, AMI-RI |
KYOUNGKI-DO, KOREA, REPUBLIC OF |
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TOWNSEND AND TOWNSEND AND CREW LLP |
HORACE H. NG |
TWO EMBARCADERO CENTER, 8TH FLOOR |
SAN FRANCISCO, CA 94111-3834 |
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