Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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05/28/2002
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Application #:
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09511327
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Filing Dt:
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02/23/2000
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Inventors:
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Masataka Watanabe, Shuichi Moriyama
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT EQUIPPED WITH FUNCTION FOR CONTROLLING THE QUANTITY OF PROCESSING PER UNIT TIME LENGTH BY DETECTING INTERNALLY ARISING DELAY
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 7-1, SHIBA 5-CHOME, MINATO-KU |
| TOKYO, JAPAN |
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| MCGINN & GIBB, P.C. |
| SEAN M. MCGINN, ESQ. |
| 1701 CLARENDON BOULEVARD, SUITE 100 |
| ARLINGTON, VA 22209 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 11-1, OSAKI 1-CHOME, SHINAGAWA-KU |
| TOKYO, JAPAN 141-0032 |
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| SUGHRUE MION, PLLC |
| 2100 PENNSYLVANIA AVENUE NW, SUITE 800 |
| WASHINGTON, DC 20037 |
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