Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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06/18/2002
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Application #:
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09769810
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Filing Dt:
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01/26/2001
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Inventors:
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James Yong Lee, Ying Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng et al
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Title:
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METHOD FOR FORMING A TRANSISTOR GATE DIELECTRIC WITH HIGH-K AND LOW-K REGIONS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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1450 MCCANDLESS DRIVE |
MILPITAS, CALIFORNIA 95035 |
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GEORGE O. SAILE |
20 MCINTOSH DRIVE |
POUGHKEEPSIE, NY 12603 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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60 WOODLANDS INDUSTRIAL PARK D |
STREET 2 |
SINGAPORE 738406, SINGAPORE |
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GEORGE O. SAILE |
28 DAVIS AVENUE |
POUGHKEEPSIE, NY 12603 |
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