Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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07/30/2002
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Application #:
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09461298
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Filing Dt:
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12/15/1999
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Publication #:
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Pub Dt:
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01/10/2002
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Inventor:
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OSAMU WADA
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Title:
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LOGIC CONSOLIDATED SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CIRCUIT AND LOGIC CIRCUIT INTEGRATED IN THE SAME CHIP
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 72 HORIKAWA-CHO, SAIWAI-KU |
| KAWASAKI-SHI, JAPAN |
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| BANNER & WITCOFF, LTD. |
| JOSEPH M. POTENZA |
| 1001 G STREET NW, 11TH FLOOR |
| WASHINGTON, DC 20001-4597 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| SARUGAKUCHO 2-8-8, CHIYODA-KU |
| TOKYO, JAPAN |
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| TOWNSEND & BANTA |
| DONALD E. TOWNSEND, JR. |
| 1225 EYE STREET N.W., SUITE 500 |
| WASHINGTON, DC 20005 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1-1, SHIBAURA 1-CHOME |
| MINATO-KU |
| TOKYO, JAPAN 105-0023 |
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| OBLON, ET AL. |
| 1940 DUKE STREET |
| ALEXANDRIA, VA 22314 |
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