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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
Issue Dt:
10/22/2002
Application #:
09574693
Filing Dt:
05/17/2000
Inventor:
David Knapp
Title:
METHOD FOR DELAY-OPTIMIZING TECHNOLOGY MAPPING OF DIGITAL LOGIC
Assignment: 1
Reel/Frame:
011051/0417Recorded: 05/17/2000Pages: 8
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
05/11/2000
Assignee:
SUITE 350
2107 N. FIRST STREET
SAN JOSE, CALIFORNIA 95131
Correspondent:
MICHAEL A. GLENN
3475 EDISON WAY, SUITE L
MENLO PARK, CA 94025
Assignment: 2
Reel/Frame:
023634/0402Recorded: 12/08/2009Pages: 6
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
12/07/2009
Assignee:
2655 SEELY AVENUE
SAN JOSE, CALIFORNIA 95134
Correspondent:
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE
SAN JOSE, CA 95134

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