Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09128057
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Filing Dt:
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07/29/1998
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Publication #:
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Pub Dt:
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11/15/2001
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Inventors:
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BRYAN TRACY, PAUL R. BESSER, MINH VAN NGO
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Title:
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METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25 MICRON AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES PRIOR TO ILD DEPOSITION AND SEMICONDUCTOR CHIP MADE THEREBY
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Assignment:
1
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SEE RECORDING AT REEL 9804, FRAME 0961. RE-RECORD TO CORRECT THE RECORDATION DATE.
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ONE AMD PLACE, M/S 68 |
SUNNYVALE, CALIFORNIA 94088 |
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LA RIVIERE GRUBMAN & PAYNE |
VICTOR FLORES |
4 JUSTIN COURT, SUITE A |
MONTEREY, CA 93940 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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D220, M/S 68 |
ONE AMD PLACE |
SUNNYVALE, CALIFORNIA 94088 |
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VICTOR FLORES |
4 JUSTIN COURT |
SUITE A |
MONTEREY, CA 93940 |
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