Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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09823723
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Filing Dt:
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03/30/2001
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Publication #:
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Pub Dt:
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10/03/2002
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Inventors:
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Alexander Levin, Ziyad Hanna, Carl Johan Seger
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Title:
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METHOD AND DEVICE FOR VERIFICATION OF VLSI DESIGNS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2200 MISSION COLLEGE BOULEVARD |
| P.O. BOX 58119 |
| SANTA CLARA, CALIFORNIA 95052-8119 |
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| KENYON & KENYON |
| GERARD A. MESSINA |
| ONE BROADWAY |
| NEW YORK, NY 10004 |
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