Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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05/27/2003
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Application #:
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09457530
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Filing Dt:
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12/09/1999
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Inventors:
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HIDESHI MAENO, TOKUYA OSAWA
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH FAULT ANALYSIS FUNCTION
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2-3, MARUNOUCHI 2-CHOME, CHIYODA-KU |
| TOKYO 100-8310, JAPAN |
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| BURNS, DOANE, SWECKER & MATHIS, L.L.P. |
| PLATON N. MANDROS |
| P.O. BOX 1404 |
| ALEXANDRIA, VIRGINIA 22313-1404 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 14A GILL STREET |
| WOBURN, MASSACHUSETTS 01801 |
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| MARK DOUMA |
| 1001 MANNING STREET |
| GREAT FALLS, VA 22066 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1753, SHIMONUMABE, NAKAHARA-KU, KAWASAKI-SHI, |
| KANAGAWA, JAPAN 211-8668 |
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| MCDERMOTT WILL & EMERY LLP |
| 600 THIRTEENTH STREET, N.W. |
| WASHINGTON, DC 20005-3096 |
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