Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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09/23/2003
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Application #:
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10152689
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Filing Dt:
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05/23/2002
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Publication #:
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Pub Dt:
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12/26/2002
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Inventors:
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Jun Ohtani, Tomoya Kawagoe
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE PROVIDED WITH A SELF-TESTING CIRCUIT FOR CARRYING OUT AN
ANALYSIS FOR REPAIR BY USING A REDUNDANT MEMORY CELL
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| CHIYODA-KU |
| 2-3, MARUNOUCHI 2-CHOME |
| TOKYO 100-8310, JAPAN |
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| MCDERMOTT, WILL & EMERY |
| STEPHEN A. BECKER |
| 600 13TH STREET, N.W. |
| WASHINGTON, D.C. 20005 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1753, SHIMONUMABE, NAKAHARA-KU, KAWASAKI-SHI, |
| KANAGAWA, JAPAN 211-8668 |
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| MCDERMOTT WILL & EMERY LLP |
| 600 THIRTEENTH STREET, N.W. |
| WASHINGTON, DC 20005-3096 |
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