Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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10/07/2003
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Application #:
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09405015
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Filing Dt:
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09/27/1999
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Inventors:
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YOSHIHIDE KOMATSU, TADAHIRO YOSHIDA, YUKIO ARIMA
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR TESTING THE SAME
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1006, OAZA KODOAM, KADOMA-SHI |
| OSAKA 571-8501, JAPAN |
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| MCDEMOTT, WILL & EMERY |
| MICHAEL E. FOGARTY, ESQ. |
| 600 13TH STREET, NW |
| WASHINGTON, DC 20005 |
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Assignment:
2
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CORRECTIVE ASSIGNMENT TO CORRECT THE ADDRESS OF THE ASSIGNEE PREVIOUSLY RECORDED ON REEL 010290 FRAME 0267.
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| 1006, OAZA KADOMA, KADOMA-SHI |
| OSAKA 571-8501, JAPAN |
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| MCDERMOTT, WILL & EMERY |
| MICHAEL E. FOGARTY, ESQ. |
| 600 13TH STREET, N.W. |
| WASHINGTON, DC 20005 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 10-23, SHINYOKOHAMA 2-CHOME, KOHOKU-KU, YOKOHAMA-SHI |
| KANAGAWA, JAPAN 2220033 |
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| PANASONIC CORPORATION |
| 2-1-61, SHIROMI, CHUO-KU |
| 7F OBP PANASONIC TOWER |
| OSAKA, 540-6207 JAPAN |
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