Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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12/02/2003
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Application #:
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09524754
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Filing Dt:
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03/14/2000
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Inventor:
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Hisataka Meguro
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Title:
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SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY TRANSISTORS WITH GATE ELECTRODES OF A DOUBLE LAYER STACKED STRUCTURE AND METHOD OF FABRICATING THE SAME
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 72 HORIKAWA-CHO, SAIWAI-KU |
| KAWASAKI-SHI, JAPAN |
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| FINNEGAN, HENDERSON, FARABOW ET AL |
| MR. ERNEST F. CHAPMAN |
| 1300 I STREET, N.W. |
| WASHINGTON, DC 20005-3315 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1-1, SHIBAURA 1-CHOME |
| MINATO-KU |
| TOKYO, JAPAN 105-0023 |
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| OBLON, ET AL. |
| 1940 DUKE STREET |
| ALEXANDRIA, VA 22314 |
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