Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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05/11/2004
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Application #:
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09699478
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Filing Dt:
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10/31/2000
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Inventors:
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Hideo Fujiwara, Toshimitsu Masuzawa, Satoshi Ohtake
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Title:
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INTEGRATED CIRCUIT WITH DESIGN FOR TESTABILITY AND METHOD FOR DESIGNING THE SAME
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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MINATO-KU |
16-10, SHINBASHI 6-CHOME |
TOKYO 105-0004, JAPAN |
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MCDERMOTT, WILL & EMERY |
STEPHEN A. BECKER |
600 13TH STREET, N.W. |
WASHINGTON, DC 20005 |
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