Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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06/29/2004
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Application #:
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09959759
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Filing Dt:
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12/03/2001
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Publication #:
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Pub Dt:
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11/21/2002
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Inventors:
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Masami Yakabe, Toshiyuki Matsumoto, Kouichi Nakano, Yoshihiro Hirota
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Title:
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IMPEDANCE DETECTION CIRCUIT, IMPEDANCE DETECTOR AND METHOD OF IMPEDANCE DETECTION
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 538 NAJIO , SHIOSE-CHO |
| NISHINOMIYA, HYOGO, JAPAN 669-1141 |
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| BARNES & THORNBURG |
| PERRY PALAN |
| 750 17TH STREET, N.W. |
| SUITE 900 |
| WASHINGTON, DC 20006 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1-8, FUSO-CHO, AMAGASAKI |
| HYOGO 660-0891, JAPAN |
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| BARNES & THORNBURG |
| PERRY PALAN |
| 750 17TH STREET, N.W. |
| STE. 900 |
| WASHINGTON, DC 20006 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 3-6, AKASAKA 5-CHOME |
| MINATO-KU, TOKYO 107-8481, JAPAN |
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| BARNES & THORNBURG |
| SUITE 900 |
| 750 17TH STREET, N.W., |
| WASHINGTON, D.C. 20006 |
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