Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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08/03/2004
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Application #:
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10051791
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Filing Dt:
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01/17/2002
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Inventors:
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Piyanuch Somchit, Precha Srisatuan, Lersak Nudach
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Title:
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PROGRAMMABLE LOGIC DEVICE VERIFICATION SYSTEM AND METHOD
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| ONE AMD PLACE P.O.BOX 3453 |
| SUNNYVALE, CALIFORNIA 94088 |
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| RENNER, OTTO, BOISSELLE & SKLAR, LLP |
| M. DAVID GALIN |
| 1621 EUCLID AVENUE, 19TH FLOOR |
| CLEVELAND OH 44115 |
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