Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10251402
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Filing Dt:
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09/20/2002
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Publication #:
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Pub Dt:
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03/25/2004
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Inventors:
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Saroj Pathak, James E. Payne, Victor V. Nguyen, Harry H. Kuo
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Title:
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HIGH SPEED ZERO DC POWER PROGRAMMABLE LOGIC DEVICE (PLD) ARCHITECTURE
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2325 ORCHARD PARKWAY |
| SAN JOSE, CALIFORNIA 95131 |
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| THOMAS SCHNECK |
| P.O. BOX 2-E |
| SAN JOSE, CA 95109-0005 |
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Assignment:
2
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PATENT SECURITY AGREEMENT
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| 1585 BROADWAY |
| NEW YORK, NEW YORK 10036 |
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| THOMAS FAHEY |
| 1025 VERMONT AVENUE NW, SUITE 1130 |
| NATIONAL CORPORATE RESEARCH, LTD. |
| WASHINGTON, DC 20005 |
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Assignment:
3
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TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL
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| 1600 TECHNOLOGY DRIVE |
| SAN JOSE, CALIFORNIA 95110 |
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| JOANNA MCCALL |
| 1025 VERMONT AVE NW, SUITE 1130 |
| NATIONAL CORPORATE RESEARCH, LTD |
| WASHINGTON, DC 20005 |
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