Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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02/01/2005
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Application #:
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10334337
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Filing Dt:
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12/30/2002
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Publication #:
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Pub Dt:
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03/04/2004
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Inventors:
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Douglas J. Bonser, Marina V. Plat, Chih Yuh Yang, Scott A. Bell, Christopher F. Lyons et al
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Title:
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METHOD FOR SEMICONDUCTOR GATE LINE DIMENSION REDUCTION
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1160 KERN AVENUE |
| SUNNYVALE, CALIFORNIA 94086-3453 |
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| FOLEY & LARDNER |
| RONALD COSLICK |
| 2029 CENTURY PARK EAST |
| LOS ANGELES, CALIFORNIA 90067-3021 |
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Assignment:
2
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AFFIRMATION OF PATENT ASSIGNMENT
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| P.O. BOX 309, UGLAND HOUSE |
| GRAND CAYMAN, CAYMAN ISLANDS KY1-1104 |
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| BNK / MHKKG |
| P.O. BOX 398 |
| AUSTIN, TX 78767-0398 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 303 TERRY FOX DRIVE |
| SUITE 300 |
| OTTAWA, CANADA K2K 3J1 |
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| ALSEPHINA INNOVATIONS INC. |
| 1891 ROBERTSON ROAD |
| SUITE 100 |
| OTTAWA, K2H 5B7 CANADA |
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