Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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03/08/2005
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Application #:
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10337827
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Filing Dt:
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01/08/2003
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Publication #:
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Pub Dt:
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03/04/2004
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Inventor:
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Takashi Inbe
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Title:
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CAPACITOR WITH VIA PLUGS FORMING FIRST AND SECOND ELECTRODES IN A MULTILAYER WIRING STRUCTURE OF A SEMICONDUCTOR DEVICE
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2-3, MARUNOUCHI 2-CHOME, CHIYODA-KU |
| TOKYO 100-8310, JAPAN |
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| OBLON, SPIVAK, MCCLELLAND, MAIER & NEUST |
| 1940 DUKE STREET |
| ALEXANDRIA, VA 22314 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 4-1, MARUNOUCHI 2-CHOME, CHIYODA-KU |
| TOKYO, JAPAN 100-6334 |
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| MCDERMOTT, WILL & EMERY |
| STEPHEN A. BECKER |
| 600 13TH STREET, N.W. |
| WASHINGTON, DC 20005-3096 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 4-1, MARUNOUCHI 2-CHOME, CHIYODA-KU |
| TOKYO, JAPAN 100-6334 |
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| MCDERMOTT, WILL & EMERY |
| STEPHEN A. BECKER |
| 600 13TH STREET, N.W. |
| WASHINGTON, DC 20005-3096 |
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