Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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03/08/2005
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Application #:
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10223316
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Filing Dt:
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08/20/2002
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Publication #:
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Pub Dt:
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03/06/2003
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Inventor:
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Shunichi Iwanari
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Title:
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MEMORY SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT IN WHICH OPERATION TIMINGS CAN BE SET EXTERNALLY
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1006, OAZA KADOMA |
| KADOMA-SHI |
| OSAKA 571-8501, JAPAN |
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| MCDERMOTT, WILL & EMERY |
| RAMYAR M. FARID |
| 600 13TH STREET, N.W. |
| WASHINGTON, DC 20005 |
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Assignment:
2
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CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
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| 1006 OAZA KADOMA, KADOMA-SHI |
| OSAKA, JAPAN 571-8501 |
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| KENJI KAMATA |
| 1130 CONNECTICUT AVE., N.W., SUITE 1100 |
| PANASONIC PATENT CENTER |
| WASHINGTON, DC 20036 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1, KOTARI-YAKEMACHI, NAGAOKAKYO-SHI, |
| KYOTO, JAPAN 617-8520 |
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| CPA GLOBAL LIMITED |
| LIBERATION HOUSE |
| CASTLE STREET |
| ST HELIER, JEI IBL JERSEY |
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