Patent Assignment Abstract of Title
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Total Assignments:
1
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2005
|
Application #:
|
10426566
|
Filing Dt:
|
04/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/04/2004
| | | | |
|
Inventors:
|
Yee-Chia Yeo, How-Yu Chen, Chien-Chao Huang, Chenming Hu, Wen-Chin Lee, Fu-Liang Yang
|
|
Title:
|
SEMICONDUCTOR-ON-INSULATOR CHIP INCORPORATING STRAINED-CHANNEL PARTIALLY-DEPLETED, FULLY-DEPLETED, AND MULTIPLE-GATE TRANSISTORS
|
|
|
Assignment:
1
|
|
|
|
|
|
|
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
|
|
|
|
|
|
|
|
|
| NO. 6, LI-HSIN RD. 6 |
| SCIENCE-BASED INDUSTRIAL PARK |
| HSIN-CHU, TAIWAN 300-77 |
|
|
|
|
| SLATER & MATSIL, L.L.P. |
| STEVEN H. SLATER |
| 17950 PRESTON RD. |
| SUITE 100 |
| DALLAS, TX 75252-5793 |
|
|
Search Results as of:
05/09/2024 07:10 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
