Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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11/22/2005
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Application #:
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10103214
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Filing Dt:
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03/21/2002
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Inventors:
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Eric G. Chambers, Tahsin Askar
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Title:
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METHOD AND APPARATUS FOR REDUCING LATENCY IN A PERIPHERAL INTERFACE CIRCUIT OF AN I/O NODE OF A COMPUTER SYSTEM
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| ONE AMD PLACE |
| SUNNYVALE, CALIFORNIA 94088 |
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| CONLEY, ROSE & TAYON, P.C. |
| B. NOEL KIVLIN |
| P. O. BOX 398 |
| AUSTIN, TX 78767-0398 |
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