Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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02/28/2006
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Application #:
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09807500
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Filing Dt:
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06/11/2001
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Inventors:
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Rakesh Malik, Puneet Goel
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Title:
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AREA EFFICIENT REALIZATION OF COEFFICIENT ARCHITECTURE FOR BIT-SERIAL FIR, IIR FILTERS AND COMBINATIONAL/SEQUENTIAL LOGIC STRUCTURE WITH ZERO LATENCY CLOCK OUTPUT
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| PARK |
| 28 ANG MO KIO INDUSTRIAL |
| 569508, SINGAPORE, SLOVENIA |
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| SEED INTELLECTUAL PROPERTY LAW GROUP |
| ERIC J. GASH |
| 701 5TH AVE, STE 6300 |
| SEATTLE, WA 98104-7092 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 28 ANG MO KIO INDUSTRIAL PARK 2 |
| 569508, SINGAPORE, SINGAPORE |
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| SECTOR 16A, INSTITUTIONAL AREA |
| NOIDA 201 301 UTTAR PRADESH, INDIA |
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| SEED INTELLECTUAL PROPERTY LAW GROUP |
| MICHAEL J. DONOHUE |
| 701 FIFTH AVENUE, SUITE 6300 |
| SEATTLE, WA 98104-7092 |
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