Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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05/02/2006
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Application #:
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10375575
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Filing Dt:
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02/27/2003
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Publication #:
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Pub Dt:
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09/02/2004
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Inventors:
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Jon Allan Faue, Harold Brett Meadows
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Title:
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INTEGRATED CIRCUIT MEMORY ARCHITECTURE WITH SELECTIVELY OFFSET DATA AND ADDRESS DELAYS TO MINIMIZE SKEW AND PROVIDE SYNCHRONIZATION OF SIGNALS AT THE INPUT/OUTPUT SECTION
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| NO. 1 CREATION ROAD 1 |
| SCIENCE-BASED INDUSTRIAL PARK |
| HSINCHU, TAIWAN R.O.C. |
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| HOGAN & HARTSON LLP |
| WILLIAM J. KUBIDA |
| ONE TABOR CENTER |
| 1200 17TH STREET, SUITE 1500 |
| DENVER, CO 80202 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 3F, NO. 19, LI-HSIN ROAD |
| SCIENCE-BASED INDUSTRIAL PARK |
| HSINCHU, TAIWAN R.O.C. |
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| HOGAN & HARTSON LLP |
| CAROL W. BURTON |
| 1200 17TH STREET, SUITE 1500 |
| DENVER, CO 80202 |
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