Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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10/31/2006
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Application #:
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10930430
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Filing Dt:
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08/31/2004
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Inventors:
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Satish R. Ganesan, Goran Bilski, Usha Prabhu, Paulo L. Dutra
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Title:
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GENERATING FAST LOGIC SIMULATION MODELS FOR A PLD DESIGN DESCRIPTION
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2100 LOGIC DRIVE |
| SAN JOSE, CALIFORNIA 95124 |
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| XILINX, INC. |
| KIM KANZAKI |
| 2100 LOGIC DRIVE |
| SAN JOSE, CA 95124 |
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