Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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05/22/2007
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Application #:
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10107297
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Filing Dt:
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03/28/2002
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Publication #:
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Pub Dt:
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01/16/2003
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Inventors:
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Hiroshi Matsushita, Kunihiro Mitsutake, Yukihiro Ushiku
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Title:
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EQUIPMENT FOR AND METHOD OF DETECTING FAULTS IN SEMICONDUCTOR INTEGRATED CIRCUITS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1-1, SHIBAURA 1-CHOME, MINATO-KU |
| TOKYO, JAPAN |
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| FINNEGAN, HENDERSON, FARABOW, ET AL |
| ERNEST F. CHAPMAN |
| 1300 I STREET, N.W. |
| WASHINGTON, D.C. 20005-3315 |
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