Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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09/04/2007
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Application #:
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11184350
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Filing Dt:
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07/19/2005
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Publication #:
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Pub Dt:
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01/25/2007
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Inventors:
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Anand Haridass, Andreas Huber, Erich Klink, Thomas Strach, Jochen Supper
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Title:
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VIA/BSM PATTERN OPTIMIZATION TO REDUCE DC GRADIENTS AND PIN CURRENT DENSITY ON SINGLE AND MULTI-CHIP MODULES
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| NEW ORCHARD ROAD |
| ARMONK, NEW YORK 10504 |
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| CASIMER K. SALYS |
| IBM CORPORATIN |
| INTELLECTUAL PROPERTY LAW |
| 11400 BURNET ROAD |
| AUSTIN, TX 78758 |
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