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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
Issue Dt:
10/09/2007
Application #:
11178565
Filing Dt:
07/12/2005
Publication #:
Pub Dt:
01/19/2006
Inventors:
Jiro Shinbo, Satoshi Arayashiki, Hirotaka Oosawa, Toshiya Uozumi, Satoru Yamamoto
Title:
SEMICONDUCTOR INTEGRATED CIRCUIT WITH PLL CIRCUIT
Assignment: 1
Reel/Frame:
018677/0596Recorded: 12/19/2006Pages: 2
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
04/25/2005
Exec Dt:
04/25/2005
Exec Dt:
04/25/2005
Exec Dt:
04/25/2005
Exec Dt:
04/25/2005
Assignee:
4-1, MARUNOUCHI 2-CHOME, CHIYODA-KU
TOKYO, JAPAN
Correspondent:
DANIEL J. STANGER
MATTINGLY, STANGER, MALUR & BRUNDIDGE
P.C.
1800 DIAGONAL ROAD, SUITE 370
ALEXANDRIA, VIRGINIA 22314
Assignment: 2
Reel/Frame:
024755/0338Recorded: 07/29/2010Pages: 54
Conveyance:
MERGER AND CHANGE OF NAME
Assignor:
Exec Dt:
04/01/2010
Assignee:
1753 SHIMONUMABE, NAKAHARA-KU
KAWASAKI-SHI, KANAGAWA, JAPAN 211-8668
Correspondent:
MATTINGLY & MALUR, P.C.
1800 DIAGONAL RD.
SUITE 370
ALEXANDRIA, VA 22314

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