Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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10/14/2008
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Application #:
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10190158
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Filing Dt:
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07/05/2002
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Publication #:
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Pub Dt:
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05/22/2003
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Inventors:
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Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka
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Title:
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DESIGNING OF A LOGIC CIRCUIT FOR TESTABILITY
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 17-2, SHIN YOKOHAMA 3-CHOME, KOUHOKU-KU, YOKOHAMA-SHI |
| KANAGAWA 222-0033, JAPAN |
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| CHRISTIE, PARKER & HALE, LLP |
| D. BRUCE PROUT |
| P.O. BOX 7068 |
| PASADENA, C.A. 91109-7068 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 8-33, MOMOCHIHAMA 3-CHOME, |
| SAWARA-KU, FUKUOKA-SHI |
| FUKUOKA, JAPAN 814-0001 |
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| CHRISTIE, PARKER & HALE, LLP |
| P.O. BOX 7068 |
| PASADENA, CA 91109-7068 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 17-2 SHIN YOKOHAMA 3-CHOME, KOUHOKU-KU, YOKOHAMA-SHI |
| KANAGAWA, JAPAN 222-0033 |
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| JOSEPHINE E. CHANG |
| P.O. BOX 7068 |
| PASADENA, CA 91109-7068 |
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