Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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04/28/2009
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Application #:
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12078643
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Filing Dt:
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04/02/2008
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Publication #:
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Pub Dt:
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09/18/2008
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Inventors:
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Isao Takayanagi, Junichi Nakamura
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Title:
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CMOS APS WITH STACKED AVALANCHE MULTIPLICATION LAYER AND LOW VOLTAGE READOUT ELECTRONICS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 8000 SOUTH FEDERAL WAY |
| BOISE, IDAHO 83706 |
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| SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC |
| 5005 E. MCDOWELL ROAD |
| MAILDROP A700 |
| PHOENIX, AZ 85008 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| C/O CITCO TRUSTEES (CAYMAN) LIMITED |
| REGATTA OFFICE PARK, WEST BAY ROAD |
| GRAND CAYMAN, CAYMAN ISLANDS Y1-1205 |
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| DICKSTEIN SHAPIRO LLP -THOMAS J. D'AMICO |
| 1825 EYE STREET N.W. |
| WASHINGTON, DC 20006 |
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