Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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06/16/2009
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Application #:
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10291508
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Filing Dt:
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11/12/2002
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Publication #:
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Pub Dt:
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05/22/2003
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Inventors:
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Yoshihiro Terashima, Hiroshi Nonoshita, Nobuyuki Yuasa
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Title:
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METHOD FOR LOGIC CHECKING TO CHECK OPERATION OF CIRCUIT TO BE CONNECTED TO BUS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 30-2, SHIMOMARUKO 3-CHOME, OHTA-KU |
| TOKYO, JAPAN |
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| FITZPATRICK, CELLA, HARPER & SCINTO |
| LOCK SEE YU-JAHNES |
| 30 ROCKEFELLER PLAZA |
| NEW YORK, NEW YORK 10112-3801 |
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