Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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08/18/2009
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Application #:
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11526881
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Filing Dt:
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09/26/2006
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Publication #:
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Pub Dt:
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04/05/2007
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Inventors:
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Tetsu Hasegawa, Chikako Tokunaga
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGN SUPPORT SOFTWARE SYSTEM AND AUTOMATIC TEST PATTERN GENERATION SYSTEM
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1-1, SHIBAURA 1-CHOME |
| MINATO-KUTOKYO, JAPAN |
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| JOSEPH M. POTENZA |
| BANNER & WITCOFF, LTD. |
| 1001 G STREET, N.W., SUITE 1100 |
| WASHINGTON, D.C. 20001-4597 |
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Assignment:
2
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REQUEST FOR CORRECTED COVER SHEET
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| 1-1, SHIBAURA 1-CHOME |
| MINATO-KU, TOKYO, JAPAN |
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| JOSEPH M. POTENZA |
| BANNER & WITCOFF, LTD. |
| 1100 13TH STREET, N.W. |
| SUITE 1200 |
| WASHINGTON, DC 20005-4051 |
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