Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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11/03/2009
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Application #:
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11513378
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Filing Dt:
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08/31/2006
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Publication #:
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Pub Dt:
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07/05/2007
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Inventors:
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Keitaro Uehara, Jun Okitsu, Yoshiki Murakami
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Title:
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CACHE COHERENCY CONTROL METHOD, CHIPSET, AND MULTI-PROCESSOR SYSTEM
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 6-6 MARUNOUCHI 1-CHOME, CHIYODA-KU |
| TOKYO, JAPAN |
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| MATTINGLY, STANGER, MALUR & BRUNDIDGE PC |
| 1800 DIAGONAL ROAD, SUITE 370 |
| ALEXANDRIA, VIRGINIA 22314 |
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