Patent Assignment Abstract of Title
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Total Assignments:
1
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2010
|
Application #:
|
11683759
|
Filing Dt:
|
03/08/2007
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2007
| | | | |
|
Inventors:
|
Kenichi Anzou, Chikako Tokunaga, Tetsu Hasegawa
|
|
Title:
|
SEMICONDUCTOR INTERGRATED CIRCUIT HAVING BUILT-N SELF TEST CIRCUIT OF LOGIC CIRCUIT AND EMBEDDED DEVICE, AND DESIGN APPARATUS THEROF
|
|
|
Assignment:
1
|
|
|
|
|
|
|
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
|
|
|
|
|
|
|
|
|
| 1-1, SHIBAURA 1-CHOME |
| MINATO-KU, TOKYO, JAPAN 105-8001 |
|
|
|
|
| AMIN, TUROCY & CALVIN, LLP |
| 24TH FLOOR, NATIONAL CITY CENTER |
| 1900 EAST NINTH STREET |
| CLEVELAND, OH 44114 |
|
|
Search Results as of:
05/21/2024 07:56 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
