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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
Issue Dt:
11/30/2010
Application #:
11907997
Filing Dt:
10/19/2007
Publication #:
Pub Dt:
04/24/2008
Inventors:
Yutaka Yoshimoto, Minoru Ito
Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING METHOD, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND ELECTRONIC DEVICE
Assignment: 1
Reel/Frame:
020631/0942Recorded: 03/11/2008Pages: 2
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
09/21/2007
Exec Dt:
09/21/2007
Assignee:
1006 OAZA KADOMA, KADOMA-SHI
OSAKA, JAPAN 571-8501
Correspondent:
KENJI KAMATA
1130 CONNECTICUT AVE., N.W., SUITE 1100
PANASONIC PATENT CENTER
WASHINGTON, DC 20036
Assignment: 2
Reel/Frame:
021897/0516Recorded: 11/20/2008Pages: 18
Conveyance:
CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
10/01/2008
Assignee:
1006 OAZA KADOMA, KADOMA-SHI
OSAKA, JAPAN 571-8501
Correspondent:
KENJI KAMATA
1130 CONNECTICUT AVE., N.W., SUITE 1100
PANASONIC PATENT CENTER
WASHINGTON, DC 20036

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