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Patent Assignment Abstract of Title
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Total Assignments: 1
Patent #:
7968272
Issue Dt:
06/28/2011
Application #:
11600198
Filing Dt:
11/16/2006
Publication #:
20070128554
Pub Dt:
06/07/2007
Inventors:
Daisuke Kawamura, Eishi Shiobara, Tomoyuki Takeishi, Kei Hayasaki, Yasunobu Onishi et al
Title:
SEMICONDUCTOR DEVICE MANUFACTURING METHOD TO FORM RESIST PATTERN.
Assignment: 1
Reel/Frame:
018909/0457Recorded: 02/12/2007Pages: 2
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
KAWAMURA, DAISUKE
Exec Dt:
11/28/2006
SHIOBARA, EISHI
Exec Dt:
12/18/2006
TAKEISHI, TOMOYUKI
Exec Dt:
12/12/2006
HAYASAKI, KEI
Exec Dt:
11/28/2006
ONISHI, YASUNOBU
Exec Dt:
11/28/2006
ITO, SHINICHI
Exec Dt:
11/29/2006
HIGASHIKI, TATSUHIKO
Exec Dt:
11/29/2006
Assignee:
KABUSHIKI KAISHA TOSHIBA
1-1, SHIBAURA 1-CHOME, MINATO-KU
TOKYO 105-8001, JAPAN
Correspondent:
FINNEGAN, HENDERSON, FARABOW, GARRETT &
LLP
901 NEW YORK AVENUE, NW
WASHINGTON, DC 20001-4413

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