Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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01/17/2012
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Application #:
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12325976
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Filing Dt:
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12/01/2008
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Inventors:
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Chaiyasit Manovit, Sridhar Narayanan, Sridhar Subramanian
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Title:
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METHOD AND SYSTEM FOR VERIFYING POWER-OPTIMIZED ELECTRONIC DESIGNS USING EQUIVALENCY CHECKING
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 3940 FREEDOM CIRCLE |
| #406 |
| SANTA CLARA, CALIFORNIA 95054 |
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| FERNANDEZ & ASSOCIATES LLP |
| 1047 EL CAMINO REAL |
| SUITE 201 |
| MENLO PARK, CA 94025 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2100 LOGIC DRIVE |
| SAN JOSE, CALIFORNIA 95124 |
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| XILINX, INC. |
| 2100 LOGIC DRIVE |
| SAN JOSE, CA 95124 |
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