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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
Issue Dt:
05/15/2012
Application #:
12401982
Filing Dt:
03/11/2009
Publication #:
Pub Dt:
09/17/2009
Inventors:
Tejaswi Gowda, Sarma Vrudhula
Title:
COMBINATIONAL EQUIVALENCE CHECKING FOR THRESHOLD LOGIC CIRCUITS
Assignment: 1
Reel/Frame:
022378/0216Recorded: 03/11/2009Pages: 4
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
03/10/2009
Exec Dt:
03/10/2009
Assignee:
1475 NORTH SCOTTSDALE ROAD
SUITE 200
SCOTTSDALE, ARIZONA 85257
Correspondent:
MCANDREWS HELD & MALLOY, LTD
500 WEST MADISON STREET
SUITE 3400
CHICAGO, IL 60661
Assignment: 2
Reel/Frame:
028226/0385Recorded: 05/17/2012Pages: 2
Conveyance:
CONFIRMATORY LICENSE (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
04/27/2012
Assignee:
4201 WILSON BLVD
ROOM 1265
ARLINGTON, VIRGINIA 22230
Correspondent:
NATIONAL SCIENCE FOUNDATION
4201 WILSON BLVD
ROOM 1265
ARLINGTON, VA 22230

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