Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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10/23/2012
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Application #:
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12339958
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Filing Dt:
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12/19/2008
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Inventors:
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Krishna Chakravadhanula, Steven L. Gregor, Brion L. Keller, Vivek Chickermane
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Title:
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FAULT MODELING FOR STATE RETENTION LOGIC
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2655 SEELY AVENUE |
| BUILDING 5 |
| SAN JOSE, CALIFORNIA 95134-1931 |
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| CADENCE DESIGN SYSTEMS, INC. C/O DUANE M |
| ATTN.: IP DOCKETING |
| 30 SOUTH 17TH STREET |
| PHILADELPHIA, PA 19103-4196 |
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