Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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05/28/2013
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Application #:
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13335338
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Filing Dt:
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12/22/2011
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Publication #:
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Pub Dt:
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04/19/2012
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Inventor:
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Toshikazu SUZUKI
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT HAVING A TEST FUNCTION FOR DETECTING A DEFECTIVE CELL.
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1006 OAZA KADOMA, KADOMA-SHI |
| OSAKA, JAPAN 571-8501 |
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| PANASONIC PATENT CENTER |
| 1130 CONNECTICUT AVE., N.W., SUITE 1100 |
| WASHINGTON, DC 20036 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 10-23, SHINYOKOHAMA 2-CHOME, KOHOKU-KU, YOKOHAMA-SHI |
| KANAGAWA, JAPAN 2220033 |
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| PANASONIC CORPORATION |
| 2-1-61, SHIROMI, CHUO-KU |
| 7F OBP PANASONIC TOWER |
| OSAKA, 540-6207 JAPAN |
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