Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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11/11/2014
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Application #:
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10774374
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Filing Dt:
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02/10/2004
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Publication #:
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Pub Dt:
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09/23/2004
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Inventors:
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Koji Kai, Tomonori Kataoka, Masayoshi Toujima
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Title:
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Integrated circuit and electric device for avoiding latency time caused by contention
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1006, OAZA KADOMA, KADOMA-SHI |
| OSAKA, 571-8501, JAPAN |
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| WENDEROTH, LIND & PONACK, LLP |
| ATTN: JEFFREY R. FILIPEK, ESQ. |
| 2033 K STREET, N.W. SUITE 800 |
| WASHINGTON, D.C. 20006-1021 |
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Assignment:
2
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CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
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| 1006 OAZA KADOMA, KADOMA-SHI |
| OSAKA, JAPAN 571-8501 |
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| KENJI KAMATA |
| 1130 CONNECTICUT AVE., N.W., SUITE 1100 |
| PANASONIC PATENT CENTER |
| WASHINGTON, DC 20036 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 10-23, SHINYOKOHAMA 2-CHOME, KOHOKU-KU, YOKOHAMA-SHI |
| KANAGAWA, JAPAN 2220033 |
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| PANASONIC CORPORATION |
| 2-1-61, SHIROMI, CHUO-KU |
| 7F OBP PANASONIC TOWER |
| OSAKA, 540-6207 JAPAN |
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