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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
9141386
Issue Dt:
09/22/2015
Application #:
12890485
Filing Dt:
09/24/2010
Publication #:
20120079233
Pub Dt:
03/29/2012
Inventors:
Jeff Wiedemeier, Sridhar Samudrala, Roger Golliver
Title:
VECTOR LOGICAL REDUCTION OPERATION IMPLEMENTED USING SWIZZLING ON A SEMICONDUCTOR CHIP
Assignment: 1
Reel/Frame:
027624/0983Recorded: 01/31/2012Pages: 8
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
WIEDEMEIER, JEFF
Exec Dt:
02/01/2011
SAMUDRALA, SRIDHAN
Exec Dt:
01/31/2011
GOLLIVER, ROGER
Exec Dt:
01/31/2011
Assignee:
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD
SANTA CLARA, CALIFORNIA 95052
Correspondent:
BLAKELY SOKOLOFF TAYLOR & ZAFMA LLP
1279 OAKMEAD PARKWAY
SUNNYVALE, CA 94085
Assignment: 2
Reel/Frame:
036179/0664Recorded: 07/24/2015Pages: 9
Conveyance:
CORRECTIVE ASSIGNMENT TO CORRECT THE SECOND ASSIGNOR'S NAME PREVIOUSLY RECORDED AT REEL: 027624 FRAME: 0983. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT.
Assignors:
WIEDEMEIER, JEFF
Exec Dt:
02/01/2011
SAMUDRALA, SRIDHAR
Exec Dt:
01/31/2011
GOLLIVER, ROGER
Exec Dt:
01/31/2011
Assignee:
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD
SANTA CLARA, CALIFORNIA 95052
Correspondent:
NICHOLSON DE VOS WEBSTER & ELLIOTT, LLP
217 HIGH STREET
PALO ALTO, CA 94301

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