Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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05/03/2016
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Application #:
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14219029
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Filing Dt:
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03/19/2014
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Publication #:
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Pub Dt:
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09/24/2015
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Inventors:
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Yao-Hsien TSAI, Chi-Ting HUANG, Cheng-Hung YEH, Hsien-Hsin Sean LEE
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Title:
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METHOD AND SYSTEM FOR VERIFYING THE DESIGN OF AN INTEGRATED CIRCUIT HAVING MULTIPLE TIERS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| NO. 8, LI-HSIN ROAD 6 |
| HSINCHU SCIENCE PARK |
| HSIN-CHU, TAIWAN 300-77 |
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| DUANE MORRIS LLP (TSMC) IP DEPARTMENT |
| 30 SOUTH 17TH STREET |
| PHILADELPHIA, PA 19103-4196 |
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