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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
Issue Dt:
05/31/2016
Application #:
14792163
Filing Dt:
07/06/2015
Publication #:
Pub Dt:
01/07/2016
Inventors:
Sarma Vrudhula, Niranjan Kulkarni, Jinghua Yang, Shimeng Yu
Title:
THRESHOLD LOGIC GATES WITH RESISTIVE NETWORKS
Assignment: 1
Reel/Frame:
037932/0252Recorded: 03/09/2016Pages: 10
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
01/07/2016
Exec Dt:
03/09/2016
Exec Dt:
03/07/2016
Exec Dt:
01/30/2016
Assignee:
1475 NORTH SCOTTSDALE ROAD
SKYSONG - SUITE 200
SCOTTSDALE, ARIZONA 85257
Correspondent:
WITHROW & TERRANOVA, PLLC
106 PINEDALE SPRINGS WAY
CARY, NC 27511
Assignment: 2
Reel/Frame:
049250/0242Recorded: 05/22/2019Pages: 2
Conveyance:
CONFIRMATORY LICENSE (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
05/13/2019
Assignee:
2415 EISENHOWER AVENUE
ROOM W 18000
ALEXANDRIA, VIRGINIA 22314
Correspondent:
NATIONAL SCIENCE FOUNDATION
2415 EISENHOWER AVENUE
ROOM W 18000
ALEXANDRIA, VA 22314

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