Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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03/28/2017
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Application #:
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15161767
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Filing Dt:
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05/23/2016
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Publication #:
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Pub Dt:
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09/15/2016
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Inventors:
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Seiji Shimabukuro, Hiroyuki Ogawa, Naoki Takeguchi, Teruyuki Mine
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Title:
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METHOD OF OPERATING MEMORY ARRAY HAVING DIVIDED APART BIT LINES AND PARTIALLY DIVIDED BIT LINE SELECTOR SWITCHES
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 951 SANDISK DRIVE |
| MILPITAS, CALIFORNIA 95035 |
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| VIERRA MAGEN MARCUS LLP |
| 575 MARKET STREET, SUITE 3750 |
| SAN FRANCISCO, CA 94105 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| TWO LEGACY TOWN CENTER |
| 6900 NORTH DALLAS PARKWAY |
| PLANO, TEXAS 75024 |
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| VIERRA MAGEN MARCUS LLP |
| 575 MARKET STREET, SUITE 3750 |
| SAN FRANCISCO, CA 94105 |
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Assignment:
3
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| 6900 DALLAS PARKWAY, SUITE 325 |
| PLANO, TEXAS 75024 |
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| VIERRA MAGEN MARCUS LLP |
| 575 MARKET STREET, SUITE 3750 |
| SAN FRANCISCO, CA 94105 |
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