Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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09754480
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Filing Dt:
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01/04/2001
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Publication #:
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Pub Dt:
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08/09/2001
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Inventors:
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John M. Boyd, Yehiel Gotkis, Rod Kistler
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Title:
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SYSTEM AND METHOD FOR POLISHING AND PLANARIZING SEMICONDUCTOR WAFERS USING REDUCED SURFACE AREA POLISHING PADS AND VARIABLE PARTIAL PAD-WAFER OVERLAPPING TECHNIQUES
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 4650 CUSHING PARKWAY |
| FREMONT, CALIFORNIA 94538 |
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| BRINKS HOFER GILSON & LIONE |
| KENT E. GENIN |
| P.O. BOX 10395 |
| CHICAGO, ILLINOIS 60610 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 3050 BOWERS AVENUE |
| SANTA CLARA, CALIFORNIA 95054-3299 |
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| PATTERSON & SHERIDAN, L.L.P. |
| 3040 POST OAK BLVD., SUITE 1500 |
| HOUSTON, TX 77056-6582 |
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