Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10035192
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Filing Dt:
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01/04/2002
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Publication #:
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Pub Dt:
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07/11/2002
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Inventor:
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Kimio Muramoto
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Title:
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Synchronization timing correcting circuit and method
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 7-1, SHIBA 5-CHOME MINATO-KU |
| TOKYO, JAPAN |
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| DICKSTEIN SHAPIRO MORIN & OSHINSKY LLP |
| MARK J. THRONSON |
| 2101 L STREET NW |
| WASHINGTON, DC 20037-1526 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1753 SHIMONUMABE, NAKAHARA-KU |
| KAWASAKI, KANAGAWA 211-8668, JAPAN |
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| STEVEN I. WEISBURD |
| DICKSTEIN SHAPIRO MORIN & OSHINSKY LLP |
| 1177 AVENUE OF THE AMERICAS 41ST FLOOR |
| ATTY. DKT.: N0029.0001 |
| NEW YORK, NY 10036-2714 |
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