Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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06/26/2007
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Application #:
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10082286
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Filing Dt:
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02/26/2002
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Publication #:
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Pub Dt:
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10/31/2002
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Inventors:
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Atsushi Takane, Haruo Yoda, Shoji Yoshida, Mitsuji Ikeda, Yasuhiko Ozawa
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Title:
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SEMICONDUCTOR INSPECTION SYSTEM
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| CHIYODA-KU, |
| 6, KANDA SURUGADAI 4-CHOME |
| TOKYO, JAPAN |
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| DICKSTEIN SHAPIRO ET AL. |
| MARK J. THRONSON |
| 2101 L STREET NW |
| WASHINGTON, DC 20037-1526 |
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Assignment:
2
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SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
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| 633 WEST FIFTH STREET, 24TH FLOOR |
| LOS ANGELES, CALIFORNIA 90071 |
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| WSGR, C/O QUI LU, SENIOR PARALEGAL |
| 650 PAGE MILL ROAD |
| FH 2-1 P12 |
| PALO ALTO, CA 94304 |
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Assignment:
3
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CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST.
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| 633 WEST FIFTH STREET, 24TH FLOOR |
| LOS ANGELES, CALIFORNIA 90071 |
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| WILSON SONSINI GOODRICH & ROSATI, P.C. |
| ONE MARKET, SPEAR TOWER, SUITE 3300 |
| SAN FRANCISCO, CA 94105 |
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