Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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08/30/2005
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Application #:
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10076809
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Filing Dt:
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02/15/2002
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Publication #:
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Pub Dt:
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10/31/2002
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Inventors:
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Vamsi Boppana, Debashis Bhattacharya
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Title:
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LOGIC CIRCUIT HAVING A FUCTIONALLY REDUNDANT TRANSISTOR NETWORK
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1671 DELL AVENUE, SUITE 206 |
| CAMPBELL, CALIFORNIA 95008 |
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| PAUL D. GREELEY, ESQ. |
| OHLANDT, GREELEY, RUGGIERO ET AL. |
| ONE LANDMARK SQUARE, 10TH FLOOR |
| STAMFORD, CONNECTICUT 06901-2682 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 490 N. MCCARTHY BOULEVARD |
| SUITE 220 |
| MILPITAS, CALIFORNIA 95035 |
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| COOLEY GODWARD KRONISH LLP, PATENT GROUP |
| FIVE PALO ALTO SQUARE |
| 3000 EL CAMINO REAL |
| PALO ALTO, CA 94306-2155 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 9255 TOWNE CENTRE DRIVE |
| SAN DIEGO, CALIFORNIA 92121-3031 |
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| COOLEY GODWARD KRONISH LLP, PATENT GROUP |
| FIVE PALO ALTO SQUARE |
| 3000 EL CAMINO REAL |
| PALO ALTO, CA 94306-2155 |
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